As a semiconductor device that amplifies high frequency power with regard to microwaves or the like, research and development are being actively pursued regarding field-effect transistors (FET) that use a group-III nitride semiconductor such as GaN or the like. In a field-effect transistor (FET) using a group-III nitride semiconductor, at a time of large signal operation a state occurs in which negative charge accumulates on a surface due to surface trap response, and a phenomenon is known that is called “current collapse” where maximum drain current degrades, or a phenomenon is known in which, at a bias point immediately after an RF power operation is turned OFF, drain current decreases to about 1/10 of the value before the power operation and a long time of a minute or longer is required for recovery (referred to below as “drain current variation after turning RF OFF”); and suppression of this transient response phenomenon has become a problem in implementing a field-effect transistor using a group-III nitride semiconductor. It is to be noted that a description of “current collapse” is given in Patent Literature 1 and a description of “drain current variation after turning RF OFF” is given in Patent Literature 2.
As a means of suppressing this transient response phenomenon, Patent Literature 3 discloses a semiconductor device provided with a GaN field-effect transistor having field plate (FP) electrodes in a region between gate and drain. FIG. 10 is a cross-sectional view schematically showing a semiconductor device having conventional field plate electrodes, as described in Patent Literature 3. In this field-effect transistor, a semiconductor layer 2 is covered by an insulating film 16 between a gate electrode 13 and a drain electrode 15, and a first field plate electrode 17 and a second field plate electrode are provided on the insulating film 16. The first field plate electrode 17 is electrically shorted to the gate electrode 13 via external wiring L1, and the second field plate electrode 18 is electrically shorted to the source electrode 14 via external wiring L2.
A field plate electrode may be used in a MOSFET or the like to relax electrical field concentration in the vicinity of a gate or between drain and source, to improve transistor breakdown voltage. A semiconductor device having a field-effect transistor provided with a field plate electrode provided to relax this electrical field concentration and improve breakdown voltage is described in Patent Literature 4 and Patent Literature 5.
Patent Literature 4 discloses a structure in which voltage applied to a field plate electrode can be increased, not by electrically shorting the field plate electrode to the gate electrode or drain electrode, but by applying a potential other than these. A description is given of a configuration of a semiconductor device disclosed in Patent Literature 4, using FIG. 11 to FIG. 13. FIG. 11 is a plane view showing modelization of the semiconductor device in question; FIG. 12 A is a cross-sectional view along section A-A, which is a field-effect transistor portion of one side in FIG. 11; FIG. 12B is a cross-sectional view along section B-B, which is an MIM capacitor part of FIG. 11; and FIG. 13 is a circuit diagram shown described by the inventor in order to explain a circuit described in Patent Literature 4.
In this field-effect transistor, MIM capacitors 18a and 18b are respectively connected to field plate electrodes 17a or 17b by outgoing lines 171a and 171b, and electrodes 183a and 183b in an intermediate layer are connected to a grounding electrode 19 by outgoing lines 191a and 191b, interposing resistors 21a or 21b respectively. Electrodes 185a and 185b in an uppermost layer are each connected to a drain electrode 13 via an inductor 20. The inductor 20 has an inductance that compensates for delay time which occurs due to the MIM capacitor 18, when a voltage waveform of the drain electrode 13 is applied to a field plate electrode 17 via the MIM capacitor 18 that is built up in two layers. The field plate electrodes 17a and 17b are formed between the gate electrodes 15a and 15b and the drain electrode 13, at a prescribed distance from these gate electrodes.
According to Patent Literature 4, by having this configuration, at a time of RF power operation, a voltage inputted from the gate electrode 15 is amplified by the field-effect transistor, and after phase inversion, appears at the drain electrode 13. Furthermore, the voltage waveform that appears at the drain electrode 13 is again inverted at the MIM capacitors 18a and 18b and applied to the field plate electrodes 17a and 17b. That is, the voltage applied to the field plate electrodes 17a and 17b at a time of RF power operation has the same phase and same amplitude as the voltage of the drain electrode 13, is maximum at a point where signal amplitude on a load line has minimum current and maximum voltage, and is minimum at a point where current is maximum and voltage is minimum. For example, there is a description that, in a case of operating at Vd s b (drain-source voltage at a bias point)=10V, voltage applied to the field plate electrode 17 has a maximum of 20V in an OFF state with minimum current and maximum voltage, and has a minimum of 0V in an ON state with maximum current and minimum voltage.
FIG. 14A shows a plane view and FIG. 14B shows a cross-sectional view F-F of a semiconductor device described in Patent Literature 5. In the conventional semiconductor device shown in FIGS. 14A and 14B, a MOSFET is provided in which are arranged a semiconductor layer 13 formed of N type silicon on a semiconductor substrate 11 with a first insulating layer 12 forming an SOI layer therebetween, with a field plate part 45b provided thereon. As shown in FIG. 14A, a drain region 42 connected to a drain electrode 49 is provided in the center of the MOSFET, and a source region 41 connected to a source electrode 48 is provided at an outermost periphery of the MOSFET. A gate electrode 45a is provided on a surface immediately inside the source region 41, with an insulating film therebetween. One end of the field plate part 45b is connected to the drain electrode 49, and the field plate part 45b goes around a drain region 42 in spiral form, with another end connected to the gate electrode 45a. The field plate part 45b is formed of material of relatively high resistance such as polycrystalline silicon, semi-insulating polycrystalline silicon or the like; the field plate part 45b itself forms a voltage dividing circuit, according to the resistance value of the field plate part 45b itself; and viewed from a direction in which a source region 41 and a drain region 42 are joined, the potential of the field plate part 45b is gradually distributed. There is a description in Patent Literature 5 that, according to the electrical field of the field plate part 45b, it is possible to gradually distribute the potential between a high potential side (a drain electrode 49 side) and a low potential side (a source electrode 48 side), and electrical field concentration can be suppressed in the semiconductor layer 13 and breakdown voltage can be improved. Patent Literature 5 also describes that the other end of the field plate part 45b may be connected to the source electrode 48 instead of the gate electrode 45a. 
[PTL 1]
International Patent Publication No. 2006/132418
[PTL 2]
Japanese Patent Kokai Publication No. JP2006-147663A
[PTL 3]
Japanese Patent Kokai Publication No. JP2005-93864A
[PTL 4]
Japanese Patent Kokai Publication No. JP2007-042813A
[PTL 5]
Japanese Patent Kokai Publication No. JP2008-227474A